Pci Express M2 Specification Revision 50 Version 10 Pdf Updated ◎

The principal update introduced by the Revision 5.0 architecture is its raw data transfer capabilities. It establishes a bit-rate of per lane, doubling the 16.0 GT/s limitations found in the previous Generation 4 iterations. Bandwidth Scaling by Lane Width x1 Lane : 4 GB/s theoretical throughput in each direction. x2 Lanes : 8 GB/s theoretical throughput in each direction.

The mainstream standard for consumer and enterprise desktop/laptop SSDs. The principal update introduced by the Revision 5